Arithmetic on Digital Logic Notebook

Half & Full Adders

Mon, 01 Jan 0001 00:00:00 +0000

Half & Full Adders#

Binary addition is just a combinational function, and it is built from one small cell repeated. That cell is the adder, and understanding it is understanding how gates do arithmetic.

The Half Adder#

A half adder adds two bits and produces a sum and a carry. The sum is 1 when the inputs differ, and the carry is 1 only when both are 1 — which is to say the sum is an XOR and the carry is an AND:

Subtractors

Mon, 01 Jan 0001 00:00:00 +0000

Subtractors#

Hardware rarely builds a dedicated subtractor, because it does not need one. Subtraction is addition of a negative number, and in two’s-complement arithmetic negating a number is nearly free — so the same adder that adds also subtracts, with a trivial change to its inputs.

Subtraction Is Addition in Disguise#

In two’s complement, a number is negated by inverting all its bits and adding 1. Therefore:

Magnitude Comparators

Mon, 01 Jan 0001 00:00:00 +0000

Magnitude Comparators#

A magnitude comparator decides the relationship between two binary numbers — whether A equals B, A is greater, or A is less. It answers in logic what a subtraction answers in arithmetic, and it is a distinct, common building block wherever hardware has to make a decision about a value.

Note: this is the digital comparator, comparing multi-bit numbers. It shares its name with the analog voltage comparator in Analog Helpers, which compares two continuous voltages and outputs a single bit — a different device for a different job.

Parity & Error Detection

Mon, 01 Jan 0001 00:00:00 +0000

Parity & Error Detection#

Parity is the cheapest integrity check in digital logic: a single extra bit that reveals whether data has been corrupted in the simplest way. It costs almost nothing to compute, which is exactly why it has been used everywhere from memory to serial links for decades.

One XOR Tree#

The parity of a group of bits is whether the count of 1s among them is odd — and that is precisely what an XOR of all the bits computes. A parity generator is therefore just an XOR tree across the data. A parity bit is appended so that the total number of 1s is always even (even parity) or always odd (odd parity), as agreed in advance.

ALU

Mon, 01 Jan 0001 00:00:00 +0000

ALU#

The Arithmetic Logic Unit is where the building blocks converge. It is a single combinational block that performs a selected operation — add, subtract, AND, OR, XOR, compare, shift — on its two operands, with function-select inputs choosing which. It is the computational core of a processor’s datapath, and it is assembled almost entirely from the primitives covered elsewhere in this section.

What It Combines#

An ALU is less an invention than an arrangement: