Gates on Digital Logic Notebook

NOT

Mon, 01 Jan 0001 00:00:00 +0000

NOT#

The NOT gate, or inverter, is the simplest logic function: its output is the complement of its input. A high in produces a low out, and a low in produces a high out.

A	NOT A
0	1
1	0

How It’s Built#

In CMOS the inverter is the most economical gate there is — one PMOS transistor pulling the output up and one NMOS pulling it down, two transistors total. A low input turns the PMOS on and pulls the output high; a high input turns the NMOS on and pulls it low. Because exactly one of the two is on in each stable state, no current flows through from supply to ground except briefly during a switch — the reason CMOS logic burns almost no static power.

AND

Mon, 01 Jan 0001 00:00:00 +0000

AND#

The AND gate outputs high only when all of its inputs are high. It is the “every condition met” gate: the output asserts precisely when nothing is missing.

A	B	A AND B
0	0	0
0	1	0
1	0	0
1	1	1

The physical picture is two switches in series: current reaches the output only when both are closed, which is exactly the behavior first built from relay contacts in series.

OR

Mon, 01 Jan 0001 00:00:00 +0000

OR#

The OR gate outputs high when any of its inputs is high. It is the “at least one condition met” gate, and the natural counterpart to AND.

A	B	A OR B
0	0	0
0	1	1
1	0	1
1	1	1

The physical picture is two switches in parallel: current reaches the output if either one is closed — the behavior built from relay contacts in parallel.

NAND

Mon, 01 Jan 0001 00:00:00 +0000

NAND#

NAND is AND followed by inversion: the output is low only when all inputs are high, and high otherwise. That small change — putting a bubble on the AND — turns out to be one of the most important facts in digital logic, because NAND can build everything else.

A	B	A NAND B
0	0	1
0	1	1
1	0	1
1	1	0

Why NAND Is Universal#

NAND is functionally complete: any Boolean function whatsoever can be built from NAND gates alone. An inverter is a NAND with its inputs tied together; an AND is a NAND followed by that inverter; an OR is a NAND with both inputs inverted — which, by De Morgan’s theorems, a NAND already is when its inputs are read as inverted. From those, every other gate and every larger function follows. A designer given nothing but NAND gates is not missing anything.

NOR

Mon, 01 Jan 0001 00:00:00 +0000

NOR#

NOR is OR followed by inversion: the output is high only when all inputs are low, and low if any input is high. Like NAND, it is a universal gate — and it holds a special place in the history of the field.

A	B	A NOR B
0	0	1
0	1	0
1	0	0
1	1	0

Universal, and the Mirror of NAND#

NOR is functionally complete: an inverter is a NOR with its inputs tied together, and every other gate follows. It is the De Morgan dual of NAND — a NOR behaves as an AND with inverted inputs — so a design can be built entirely from NOR just as it can be built entirely from NAND. In CMOS it is equally native and cheap: four transistors for a two-input gate, where a true OR needs six.

XOR

Mon, 01 Jan 0001 00:00:00 +0000

XOR#

The exclusive-OR gate outputs high when its inputs differ and low when they match. Where OR asks “is any input high?”, XOR asks “is exactly an odd number of inputs high?” — for two inputs, “are they different?”

A	B	A XOR B
0	0	0
0	1	1
1	0	1
1	1	0

The Difference Detector#

XOR is fundamentally a difference detector, and two identities make it far more useful than that description suggests:

XNOR

Mon, 01 Jan 0001 00:00:00 +0000

XNOR#

XNOR is the complement of XOR: its output is high when its inputs match and low when they differ. If XOR is the difference detector, XNOR is the equality detector.

A	B	A XNOR B
0	0	1
0	1	0
1	0	0
1	1	1

Equality in One Gate#

XNOR answers “are these two bits the same?” directly — a single gate that is high precisely when A equals B. Because it is XOR inverted, it shares XOR’s cost and its complementary identities: A XNOR 0 = NOT A and A XNOR 1 = A, so it too can act as a controlled inverter, just with the opposite sense to XOR.

Schmitt Trigger

Mon, 01 Jan 0001 00:00:00 +0000

Schmitt Trigger#

A Schmitt trigger is not a new logic function — it is usually just an inverter or buffer — but a special input characteristic: hysteresis. Instead of one switching threshold, it has two, and which one is active depends on which way the input is currently moving. That small change is what lets logic accept slow, noisy, or sloppy signals and still produce clean edges.

Two Thresholds Instead of One#

An ordinary gate has a single threshold, and any wobble of the input around that level produces a burst of output transitions. A Schmitt-trigger input has an upper threshold (V_T+) and a lower threshold (V_T−), with a gap between them: