Storage on Digital Logic Notebook

SR Latch

Mon, 01 Jan 0001 00:00:00 +0000

SR Latch#

The SR (set-reset) latch is the simplest memory element, and it is the seed from which every latch, flip-flop, and register grows. Cross-couple two gates so that each one’s output feeds back into the other’s input, and the pair becomes bistable: it has two stable states and will rest in whichever one it was last driven into, holding that state after the driving input is removed. That feedback loop is what “remembering” means in hardware.

D Latch

Mon, 01 Jan 0001 00:00:00 +0000

D Latch#

The D latch fixes the two awkward things about the raw SR latch: its forbidden state, and its lack of any control over when it listens. It does this by adding a single data input D and an enable, arranged so that set and reset can never be asserted at the same time.

Transparent When Enabled#

Steering logic drives the internal set/reset from D and its complement, gated by the enable. The result is simple to state:

D Flip-Flop

Mon, 01 Jan 0001 00:00:00 +0000

D Flip-Flop#

The D flip-flop is the workhorse of sequential logic — the element behind essentially every register, counter, shift register, state machine, and pipeline stage in a modern design. It stores one bit, and it captures that bit at a single, well-defined instant: the clock edge.

Edge-Triggered, Not Level-Sensitive#

This is the one distinction that matters. A D latch is transparent — its output follows D the whole time it is enabled. A D flip-flop instead samples D only at the rising (or falling) edge of the clock and holds that value for the entire cycle until the next edge, ignoring anything D does in between.

JK Flip-Flop

Mon, 01 Jan 0001 00:00:00 +0000

JK Flip-Flop#

The JK flip-flop is the SR latch’s clocked, well-behaved descendant — and, for the discrete-logic era, its most versatile one. It takes SR’s set and reset inputs (here called J and K) but replaces the forbidden “both asserted” combination with something useful: toggle.

J	K	Q (next)
0	0	Q — hold
1	0	1 — set
0	1	0 — reset
1	1	Q̄ — toggle

With J and K both high, each clock edge flips the output. That closes the one gap SR left open and makes a single flip-flop able to hold, set, reset, or toggle depending only on how its inputs are wired.

T Flip-Flop

Mon, 01 Jan 0001 00:00:00 +0000

T Flip-Flop#

The T (toggle) flip-flop does one thing: when its T input is high, it flips state on every clock edge; when T is low, it holds. That single behavior makes it the building block of counters and frequency dividers.

T	Q (next)
0	Q — hold
1	Q̄ — toggle

Divide by Two#

A flip-flop that toggles on each clock edge produces an output that changes half as often as its clock — a divide-by-two. Feed that output into the clock of a second toggle stage and it divides by two again; chain n stages and the result counts in binary and divides the input frequency by 2ⁿ. That is precisely how a ripple counter works, and why the T flip-flop lives at the root of the counting primitives.

Registers

Mon, 01 Jan 0001 00:00:00 +0000

Registers#

A register is simply a row of D flip-flops sharing one clock, storing an N-bit word instead of a single bit. Where a flip-flop remembers a bit, a register remembers a number — and that makes it the basic unit of storage in any datapath.

A Word, Captured on a Clock#

Present a word at the register’s inputs, pulse the clock, and all N bits are captured together and held until the next clock — the same edge-triggered capture as a single flip-flop, widened. Because every bit latches on the same edge, the stored word is always internally consistent; there is no moment where half the bits are old and half are new. The classic octal parts are the 74HC574 and 74HC377 (eight D flip-flops with a shared clock, the latter with a load enable).