Glossary#

Terms and definitions used throughout this notebook. Hover over a highlighted term on any other page to see its definition inline, or browse the full list below.

ALU: Arithmetic Logic Unit — a combinational block that performs a selected arithmetic or logic operation (add, subtract, AND, OR, compare) on its operands. The computational core of a CPU datapath; the 74181 was the classic discrete example.
Boolean algebra: The algebra of two-valued logic (true/false, 1/0) using AND, OR, and NOT. Its identities let a logic expression be manipulated and simplified before it is committed to gates.
clock domain crossing: Passing a signal between two circuits clocked by unrelated (asynchronous) clocks. Requires a synchronizer or handshake to avoid metastability-induced failures.
CMOS: Complementary Metal-Oxide-Semiconductor — a logic family using complementary p- and n-channel MOSFETs that draws negligible static power and came to dominate digital integrated circuits.
combinational logic: Logic whose outputs depend only on the present inputs, with no internal memory of past state. Gates, multiplexers, and decoders are combinational.
CPLD: Complex Programmable Logic Device — non-volatile programmable logic built from a handful of PAL-like blocks with a central interconnect. Sits between simple PLDs and FPGAs in capacity, with predictable timing and instant-on operation.
De Morgan's theorems: Two identities linking AND, OR, and inversion: NOT(A AND B) = NOT A OR NOT B, and NOT(A OR B) = NOT A AND NOT B. They are why NAND and NOR are each functionally complete.
fan-out: The number of gate inputs a single output can drive while keeping logic levels and timing within spec. Exceeding it slows edges and erodes noise margin.
finite state machine: A sequential circuit that occupies one of a finite set of states and moves between them based on inputs, computing outputs from the current state (and, in a Mealy machine, the inputs). The general form of all sequential logic.
flip-flop: A single-bit storage element that holds one of two stable states and changes only on a defined trigger, usually a clock edge. The basic building block of sequential logic.
FPGA: Field-Programmable Gate Array — an integrated circuit whose logic function is defined after manufacture by loading a configuration, typically built from a fabric of lookup tables, flip-flops, and programmable interconnect.
full adder: A one-bit adder with carry-in and carry-out, summing three bits. Chaining N full adders yields an N-bit ripple-carry adder — the basis of hardware arithmetic.
HDL: Hardware Description Language — a language such as Verilog or VHDL that describes digital logic behaviorally or structurally, then synthesized into gates for an FPGA, CPLD, or ASIC.
hold time: The interval after a clock edge during which a flip-flop's data input must remain stable. Like setup time, violating it risks metastability.
Karnaugh map: A grid arrangement of a truth table, ordered so adjacent cells differ by one variable, used to minimize a Boolean function by grouping adjacent 1s. Practical up to about four to six variables.
Mealy machine: A finite state machine whose outputs depend on both the current state and the current inputs, allowing faster response than a Moore machine at the cost of possible output glitches.
metastability: A flip-flop's temporary residence in an undefined region between valid logic levels after a setup/hold violation. It resolves to a valid level after an unbounded time, which is why synchronizers are needed at clock-domain boundaries.
Moore machine: A finite state machine whose outputs depend only on the current state, not directly on the inputs. Outputs are glitch-free and change only after a state transition.
PLD: Programmable Logic Device — a chip whose logic function is set by the user, historically via a programmable AND/OR array (PAL, GAL). The ancestor of the CPLD and FPGA.
propagation delay: The time between a change at a logic element's input and the resulting change at its output. Accumulated propagation delay along a path sets the maximum usable clock speed.
sequential logic: Logic whose outputs depend on both present inputs and stored internal state, so behavior is a function of history. Flip-flops, registers, and state machines are sequential.
setup time: The interval before a clock edge during which a flip-flop's data input must be stable. Violating it can drive the flip-flop into a metastable state.
TTL: Transistor–Transistor Logic — a bipolar-transistor logic family that dominated small- and medium-scale integration from the late 1960s, defining conventions for logic levels and part numbering (the 7400 series) that outlived the technology itself.