<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>⚙️ Evolution of Implementation on Digital Logic Notebook</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/</link><description>Recent content in ⚙️ Evolution of Implementation on Digital Logic Notebook</description><generator>Hugo</generator><language>en-us</language><atom:link href="https://applied-ee.github.io/digital-logic-notebook/docs/implementation/index.xml" rel="self" type="application/rss+xml"/><item><title>RTL</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/rtl/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/rtl/</guid><description>&lt;h1 id="rtl"&gt;RTL&lt;a class="anchor" href="#rtl"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;Resistor-Transistor Logic was the first practical way to build logic gates inside an integrated circuit. Its name is its schematic: resistors at the inputs, a &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/before-the-ic/transistors/"&gt;transistor&lt;/a&gt; doing the switching. It is obsolete now, but it is where the family tree starts, and every weakness of RTL is the reason the next family exists.&lt;/p&gt;
&lt;h2 id="how-its-built"&gt;How It&amp;rsquo;s Built&lt;a class="anchor" href="#how-its-built"&gt;#&lt;/a&gt;&lt;/h2&gt;
&lt;p&gt;The basic RTL gate is a &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/building-blocks/gates/nor/"&gt;NOR&lt;/a&gt;. Each input drives the base of its own transistor through a resistor; all the transistors share a single collector resistor to the supply. If &lt;em&gt;any&lt;/em&gt; input is high, its transistor conducts and pulls the shared output low — low-when-any-input-is-high is exactly NOR. Adding transistors in parallel adds inputs; that is the entire trick.&lt;/p&gt;</description></item><item><title>DTL</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/dtl/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/dtl/</guid><description>&lt;h1 id="dtl"&gt;DTL&lt;a class="anchor" href="#dtl"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;Diode-Transistor Logic answered &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/implementation/rtl/"&gt;RTL&lt;/a&gt;&amp;rsquo;s weaknesses by changing what does the logic at the input: diodes instead of resistors. It is also obsolete, but it is the most instructive stop in the lineage, because understanding DTL is understanding exactly what problem &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/implementation/ttl/"&gt;TTL&lt;/a&gt; then solved.&lt;/p&gt;
&lt;h2 id="how-its-built"&gt;How It&amp;rsquo;s Built&lt;a class="anchor" href="#how-its-built"&gt;#&lt;/a&gt;&lt;/h2&gt;
&lt;p&gt;DTL splits the work in two. A network of &lt;strong&gt;diodes&lt;/strong&gt; at the input performs the combinational logic — several diodes into a common node form an AND — and a &lt;strong&gt;transistor&lt;/strong&gt; stage behind it inverts and restores the signal to a clean level. Diode-AND followed by transistor-inversion is a &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/building-blocks/gates/nand/"&gt;NAND&lt;/a&gt;, the characteristic DTL gate.&lt;/p&gt;</description></item><item><title>TTL</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/ttl/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/ttl/</guid><description>&lt;h1 id="ttl"&gt;TTL&lt;a class="anchor" href="#ttl"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;Transistor-Transistor Logic was the family that made integrated logic ubiquitous. For roughly two decades it was simply what &amp;ldquo;a logic chip&amp;rdquo; meant, and although &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/implementation/cmos/"&gt;CMOS&lt;/a&gt; has replaced it in almost every new design, TTL&amp;rsquo;s conventions — its part numbers and its voltage levels — are so deeply embedded that they still govern logic built today.&lt;/p&gt;
&lt;h2 id="how-its-built"&gt;How It&amp;rsquo;s Built&lt;a class="anchor" href="#how-its-built"&gt;#&lt;/a&gt;&lt;/h2&gt;
&lt;p&gt;TTL took &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/implementation/dtl/"&gt;DTL&lt;/a&gt; and replaced its two weak spots. The string of input diodes became a single &lt;strong&gt;multi-emitter transistor&lt;/strong&gt;: each emitter is an input, and the transistor actively sweeps charge out of the following stage, switching far faster than passive diodes could. The passive pull-up became a &lt;strong&gt;totem-pole output&lt;/strong&gt; — a stacked pair of transistors that actively drives the output both high and low, giving fast edges and real drive strength. The signature gate is the 7400 quad two-input &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/building-blocks/gates/nand/"&gt;NAND&lt;/a&gt;.&lt;/p&gt;</description></item><item><title>CMOS</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/cmos/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/cmos/</guid><description>&lt;h1 id="cmos"&gt;CMOS&lt;a class="anchor" href="#cmos"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;Complementary Metal-Oxide-Semiconductor logic is the milestone the whole lineage was building toward. Every other family on this list is either an ancestor of CMOS or a variety of it, and every integrated circuit in a modern device — processor, memory, FPGA, microcontroller — is CMOS underneath. It won on the one axis that ultimately mattered most: power.&lt;/p&gt;
&lt;h2 id="how-its-built"&gt;How It&amp;rsquo;s Built&lt;a class="anchor" href="#how-its-built"&gt;#&lt;/a&gt;&lt;/h2&gt;
&lt;p&gt;A CMOS gate uses two complementary networks between the output and the rails: a &lt;strong&gt;PMOS&lt;/strong&gt; network that can pull the output high and an &lt;strong&gt;NMOS&lt;/strong&gt; network that can pull it low, arranged so that in any stable input state &lt;em&gt;exactly one&lt;/em&gt; network conducts. Because there is never a path from supply to ground in a settled state, a CMOS gate draws essentially &lt;strong&gt;no static current&lt;/strong&gt; — it dissipates power only briefly while switching, charging and discharging capacitance.&lt;/p&gt;</description></item><item><title>HC / HCT Families</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/hc-hct/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/hc-hct/</guid><description>&lt;h1 id="hc--hct-families"&gt;HC / HCT Families&lt;a class="anchor" href="#hc--hct-families"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;The 74HC and 74HCT families are where &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/implementation/cmos/"&gt;CMOS&lt;/a&gt; became the &lt;em&gt;practical default&lt;/em&gt; for board-level logic. They pair CMOS power consumption with speed comparable to the popular &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/implementation/ttl/"&gt;74LS TTL&lt;/a&gt; of their day, wrapped in the familiar 74xx part numbers — which is why, for a great deal of discrete digital design, &amp;ldquo;HC&amp;rdquo; is simply the logic reached for first.&lt;/p&gt;
&lt;h2 id="high-speed-cmos"&gt;High-Speed CMOS&lt;a class="anchor" href="#high-speed-cmos"&gt;#&lt;/a&gt;&lt;/h2&gt;
&lt;p&gt;74&lt;strong&gt;HC&lt;/strong&gt; (&amp;ldquo;High-speed CMOS&amp;rdquo;) is silicon-gate CMOS built to be fast enough to replace LS-TTL while keeping CMOS&amp;rsquo;s near-zero static power, its wide 2–6 V supply range, and its high, rail-to-rail noise margin (thresholds near half the supply). Functionally it carries the entire 74xx catalog forward: a 74HC00 is the CMOS quad NAND, a 74HC595 the CMOS shift register, and so on.&lt;/p&gt;</description></item><item><title>LVC / AHC</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/lvc-ahc/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/lvc-ahc/</guid><description>&lt;h1 id="lvc--ahc"&gt;LVC / AHC&lt;a class="anchor" href="#lvc--ahc"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;As supply voltages fell — 5 V giving way to 3.3 V, then 1.8 V and below, for both power savings and speed — logic families followed them down. LVC, AHC, and their many siblings are &lt;strong&gt;today&amp;rsquo;s&lt;/strong&gt; discrete logic: the parts actually specified in current designs, where &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/implementation/hc-hct/"&gt;HC/HCT&lt;/a&gt; is increasingly the legacy 5 V choice.&lt;/p&gt;
&lt;h2 id="todays-low-voltage-cmos"&gt;Today&amp;rsquo;s Low-Voltage CMOS&lt;a class="anchor" href="#todays-low-voltage-cmos"&gt;#&lt;/a&gt;&lt;/h2&gt;
&lt;p&gt;These are all &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/implementation/cmos/"&gt;CMOS&lt;/a&gt;, refined for lower voltages, higher speed, and mixed-voltage systems:&lt;/p&gt;</description></item><item><title>Tiny Logic (74LVC1Gxx)</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/tiny-logic/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/digital-logic-notebook/docs/implementation/tiny-logic/</guid><description>&lt;h1 id="tiny-logic-74lvc1gxx"&gt;Tiny Logic (74LVC1Gxx)&lt;a class="anchor" href="#tiny-logic-74lvc1gxx"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;Tiny logic is the endpoint of discrete-logic miniaturization: &lt;strong&gt;one gate per package&lt;/strong&gt;. Where the classic 7400 put four NAND gates in a 14-pin package, a part like the 74LVC1G00 is a single two-input NAND in a five-pin package smaller than a grain of rice. It is the most modern link in this chapter, and it exists because of what happened to logic everywhere else in the notebook.&lt;/p&gt;</description></item></channel></rss>