<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>🚀 The Modern World on Digital Logic Notebook</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/</link><description>Recent content in 🚀 The Modern World on Digital Logic Notebook</description><generator>Hugo</generator><language>en-us</language><atom:link href="https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/index.xml" rel="self" type="application/rss+xml"/><item><title>Microcontrollers</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/microcontrollers/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/microcontrollers/</guid><description>&lt;h1 id="microcontrollers"&gt;Microcontrollers&lt;a class="anchor" href="#microcontrollers"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;A microcontroller is a whole small computer on one chip: a CPU, its memory (flash for the program, RAM for data), and a set of peripherals, all on a single die. For most small systems it is the first and most common answer to the question this chapter asks — &lt;em&gt;where did the logic go?&lt;/em&gt; It went into a program running on a cheap MCU.&lt;/p&gt;
&lt;h2 id="logic-that-became-a-program"&gt;Logic That Became a Program&lt;a class="anchor" href="#logic-that-became-a-program"&gt;#&lt;/a&gt;&lt;/h2&gt;
&lt;p&gt;The peripherals around an MCU&amp;rsquo;s CPU are, quite literally, the &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/building-blocks/"&gt;functional building blocks&lt;/a&gt; of this book absorbed onto the die and made software-configurable. A timer/counter peripheral is a &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/building-blocks/counting/"&gt;counter&lt;/a&gt; — a 7490 that moved inside the chip. A UART or SPI block is &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/building-blocks/moving-data/shift-registers/"&gt;shift registers&lt;/a&gt; plus a small &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/building-blocks/state-machines/"&gt;state machine&lt;/a&gt;. GPIO is latches and buffers. Where a 1975 design wired those functions together from 74xx parts, an MCU design configures them in firmware and wires them with lines of code.&lt;/p&gt;</description></item><item><title>PLDs &amp; CPLDs</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/plds-cplds/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/plds-cplds/</guid><description>&lt;h1 id="plds--cplds"&gt;PLDs &amp;amp; CPLDs&lt;a class="anchor" href="#plds--cplds"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;Programmable logic devices are the step between fixed-function chips and the &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/fpgas/"&gt;FPGA&lt;/a&gt;: user-defined logic without custom silicon. They exist to answer a specific frustration — a board covered in 74xx glue that has to be redesigned every time the logic changes — by putting that glue into a single part whose function is programmed, not wired.&lt;/p&gt;
&lt;h2 id="from-pal-to-gal-to-cpld"&gt;From PAL to GAL to CPLD&lt;a class="anchor" href="#from-pal-to-gal-to-cpld"&gt;#&lt;/a&gt;&lt;/h2&gt;
&lt;p&gt;The original &lt;strong&gt;PLDs&lt;/strong&gt; implemented logic as a programmable &lt;strong&gt;sum-of-products&lt;/strong&gt; array: a grid of AND terms feeding OR terms, with fuses (PAL) or reprogrammable cells (GAL) selecting which connections are made. Because any Boolean function can be written in &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/building-blocks/boolean-foundations/canonical-forms/"&gt;sum-of-products form&lt;/a&gt;, that one structure can implement a wide range of combinational logic — and with a flip-flop on each output, small state machines too. A single GAL could swallow a fistful of gates, decoders, and latches.&lt;/p&gt;</description></item><item><title>FPGAs</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/fpgas/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/fpgas/</guid><description>&lt;h1 id="fpgas"&gt;FPGAs&lt;a class="anchor" href="#fpgas"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;A Field-Programmable Gate Array is the &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/building-blocks/"&gt;building blocks&lt;/a&gt; of this book made configurable: a fabric of logic and flip-flops whose function is defined after manufacture by loading a configuration. Where a &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/microcontrollers/"&gt;microcontroller&lt;/a&gt; turns logic into a sequential program, an FPGA turns it into actual parallel hardware — every part of the design runs at once, the way discrete logic always did.&lt;/p&gt;
&lt;h2 id="a-fabric-of-lookup-tables-and-flip-flops"&gt;A Fabric of Lookup Tables and Flip-Flops&lt;a class="anchor" href="#a-fabric-of-lookup-tables-and-flip-flops"&gt;#&lt;/a&gt;&lt;/h2&gt;
&lt;p&gt;The fabric is made of many small configurable blocks, each holding a &lt;strong&gt;lookup table (LUT)&lt;/strong&gt; and a &lt;strong&gt;flip-flop&lt;/strong&gt;, tied together by a mesh of programmable interconnect and surrounded by configurable I/O.&lt;/p&gt;</description></item><item><title>HDL Concepts</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/hdl-concepts/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/hdl-concepts/</guid><description>&lt;h1 id="hdl-concepts"&gt;HDL Concepts&lt;a class="anchor" href="#hdl-concepts"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;A hardware description language — Verilog or VHDL — is how logic is actually specified once there is too much of it to draw. Nobody schematics a million gates; instead they &lt;em&gt;describe&lt;/em&gt; the intended behavior in an HDL, and a synthesis tool turns that description into real gates and flip-flops, whether for an &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/fpgas/"&gt;FPGA&lt;/a&gt;&amp;rsquo;s fabric or an &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/asics/"&gt;ASIC&lt;/a&gt;&amp;rsquo;s cells.&lt;/p&gt;
&lt;h2 id="it-describes-hardware-it-does-not-run"&gt;It Describes Hardware, It Does Not Run&lt;a class="anchor" href="#it-describes-hardware-it-does-not-run"&gt;#&lt;/a&gt;&lt;/h2&gt;
&lt;p&gt;The single most important idea — and the one that trips up newcomers from software — is that &lt;strong&gt;an HDL describes hardware that all exists at once; it is not a program that executes line by line.&lt;/strong&gt; When a Verilog file says one signal is the AND of two others and, elsewhere, that a third is the OR of two more, both pieces of logic are built and both operate concurrently, forever. There is no &amp;ldquo;first this, then that.&amp;rdquo; Order of appearance is irrelevant; everything is simultaneous, because it is describing wires and gates, not instructions.&lt;/p&gt;</description></item><item><title>ASICs</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/asics/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/asics/</guid><description>&lt;h1 id="asics"&gt;ASICs&lt;a class="anchor" href="#asics"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;An Application-Specific Integrated Circuit is custom silicon: the logic of a design fixed permanently into a chip made for one purpose. It is the &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/building-blocks/"&gt;building blocks&lt;/a&gt; of this book laid out in silicon at scale — millions or billions of gates and flip-flops, placed once and never changed.&lt;/p&gt;
&lt;h2 id="the-primitives-fixed-in-silicon"&gt;The Primitives, Fixed in Silicon&lt;a class="anchor" href="#the-primitives-fixed-in-silicon"&gt;#&lt;/a&gt;&lt;/h2&gt;
&lt;p&gt;Most ASICs are built from a &lt;strong&gt;standard-cell library&lt;/strong&gt;: a catalog of pre-designed, pre-characterized layouts for each primitive — a NAND cell, a NOR cell, a D &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/building-blocks/storage/"&gt;flip-flop&lt;/a&gt; cell, a full-adder cell, and so on. That library is nothing more than the &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/building-blocks/gates/"&gt;gates&lt;/a&gt; of Part II rendered as physical geometry. A designer writes the logic in an &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/hdl-concepts/"&gt;HDL&lt;/a&gt;, synthesis maps it onto those cells, and place-and-route tools arrange and wire millions of them across the die. (Gate arrays and full-custom design are the other, less common points on the spectrum, trading flexibility for effort.)&lt;/p&gt;</description></item><item><title>SoCs</title><link>https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/socs/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/socs/</guid><description>&lt;h1 id="socs"&gt;SoCs&lt;a class="anchor" href="#socs"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;A System on a Chip is integration taken to its conclusion: not just logic, and not just a processor, but a whole system on one die. Where a &lt;a href="https://applied-ee.github.io/digital-logic-notebook/docs/modern-world/microcontrollers/"&gt;microcontroller&lt;/a&gt; put a CPU, memory, and simple peripherals together, an SoC adds everything else a product needs — multiple CPU cores, a GPU, a neural accelerator, memory controllers, high-speed I/O, radios, image and signal processors — onto a single piece of silicon.&lt;/p&gt;</description></item></channel></rss>