⏱️ Timing & the Real World on Digital Logic Notebook

Propagation Delay & Fan-Out

Mon, 01 Jan 0001 00:00:00 +0000

Propagation Delay & Fan-Out#

The first crack in the ideal picture is that a gate does not respond instantly. Propagation delay is the time between an input changing and the output following — a few nanoseconds for ordinary logic, but never zero. Every timing limit in a digital system traces back to this one fact.

Delay Accumulates Along a Path#

Delays add up along a chain of gates. A signal passing through five gates arrives roughly five gate-delays late, and the critical path — the slowest route from one register to the next — sets how fast the whole circuit can run. This is why a ripple counter and a ripple-carry adder slow down as they get wider: the carry has to propagate stage by stage, and nothing downstream is valid until it arrives. It is also why hazards and glitches exist at all — two paths of unequal delay reconverging produce a transient wrong value. Shortening the critical path, by using fewer levels of logic or faster carry schemes, is how a design is made to run faster.

Setup & Hold Time

Mon, 01 Jan 0001 00:00:00 +0000

Setup & Hold Time#

A flip-flop captures its data input at the clock edge, but only if that data is stable in a narrow window around the edge. Setup time is how long the data must be steady before the edge; hold time is how long it must remain steady after. Meet both and the flip-flop captures a clean value; violate either and it can go metastable. These two numbers are the foundation on which all synchronous timing rests.

Clocks & Distribution

Mon, 01 Jan 0001 00:00:00 +0000

Clocks & Distribution#

The clock is the heartbeat that keeps a synchronous system in step: every flip-flop updates on its edge, so the whole machine advances together. That only works if a clean edge reaches every flip-flop at very nearly the same instant — which is harder than it sounds, and where a surprising amount of real-world timing trouble lives.

Where Clocks Come From#

A clock starts at an oscillator. A crystal oscillator gives an accurate, stable frequency and is the reference for anything that must keep real time or talk to the outside world. Cheaper RC or ring oscillators are built from an inverter and a delay, trading precision for cost — the Schmitt-trigger relaxation oscillator is the simplest example. A PLL multiplies or divides a reference to synthesize the several frequencies a modern chip needs, and simple frequency dividers derive slower clocks from a fast one.

Metastability & Synchronizers

Mon, 01 Jan 0001 00:00:00 +0000

Metastability & Synchronizers#

When a flip-flop’s setup or hold window is violated — its data changes right at the clock edge — it may not cleanly capture a 0 or a 1. Instead it can enter metastability: an unstable in-between condition where the output hovers at an invalid level, or oscillates, before eventually settling to one value or the other. This is the sharpest way the digital abstraction breaks, and it cannot be designed away — only managed.

Clock Domain Crossing

Mon, 01 Jan 0001 00:00:00 +0000

Clock Domain Crossing#

A modern chip does not run on one clock. A processor core, a memory interface, a radio, and a USB port each have their own, and signals constantly have to pass between them. Whenever a signal generated in one clock domain is sampled by another whose clock is unrelated, it is a clock domain crossing (CDC) — and it is where metastability stops being a curiosity and becomes a design discipline.