Digital Logic Notebook

📖 Preface

Mon, 01 Jan 0001 00:00:00 +0000

Preface#

Modern digital hardware is easy to use without understanding. A logic gate, a flip-flop, a lookup table in an FPGA — all can be dropped into a design as black boxes that simply behave. But the shape of those black boxes is not arbitrary. Every one of them carries the fingerprints of the technology it replaced and the constraints that technology lived under.

This notebook exists to make that lineage visible.

Comparators

Mon, 01 Jan 0001 00:00:00 +0000

Comparators#

A comparator is the doorway from the analog world into the digital one. It looks at two analog voltages and produces a single logic bit: high if the positive input is above the negative input, low otherwise. Every threshold decision a digital system makes about a continuous signal — is the battery low, has the sensor crossed a level, did the waveform cross zero — starts at a comparator.

Decoder

Mon, 01 Jan 0001 00:00:00 +0000

Decoder#

A decoder takes an n-bit binary code and activates exactly one of its 2ⁿ outputs — the one whose number matches the input. A 3-bit input picks one of eight outputs, a 4-bit input one of sixteen. It turns a compact binary number into a one-hot signal: “this specific one, and no other.”

Every Output Is a Minterm#

Internally, each output is an AND of the input bits in a particular true/complemented combination — output 5 of a 3-to-8 decoder is high only for the input 101. That combination is a minterm, so a decoder generates all the minterms of its inputs at once. Because any Boolean function is a sum of the minterms where it is true (its sum-of-products form), a decoder plus a single OR gate can build any function of its input variables — which is one reason decoders show up far beyond their obvious use.

Half & Full Adders

Mon, 01 Jan 0001 00:00:00 +0000

Half & Full Adders#

Binary addition is just a combinational function, and it is built from one small cell repeated. That cell is the adder, and understanding it is understanding how gates do arithmetic.

The Half Adder#

A half adder adds two bits and produces a sum and a carry. The sum is 1 when the inputs differ, and the carry is 1 only when both are 1 — which is to say the sum is an XOR and the carry is an AND:

Microcontrollers

Mon, 01 Jan 0001 00:00:00 +0000

Microcontrollers#

A microcontroller is a whole small computer on one chip: a CPU, its memory (flash for the program, RAM for data), and a set of peripherals, all on a single die. For most small systems it is the first and most common answer to the question this chapter asks — where did the logic go? It went into a program running on a cheap MCU.

Logic That Became a Program#

The peripherals around an MCU’s CPU are, quite literally, the functional building blocks of this book absorbed onto the die and made software-configurable. A timer/counter peripheral is a counter — a 7490 that moved inside the chip. A UART or SPI block is shift registers plus a small state machine. GPIO is latches and buffers. Where a 1975 design wired those functions together from 74xx parts, an MCU design configures them in firmware and wires them with lines of code.

NOT

Mon, 01 Jan 0001 00:00:00 +0000

NOT#

The NOT gate, or inverter, is the simplest logic function: its output is the complement of its input. A high in produces a low out, and a low in produces a high out.

A	NOT A
0	1
1	0

How It’s Built#

In CMOS the inverter is the most economical gate there is — one PMOS transistor pulling the output up and one NMOS pulling it down, two transistors total. A low input turns the PMOS on and pulls the output high; a high input turns the NMOS on and pulls it low. Because exactly one of the two is on in each stable state, no current flows through from supply to ground except briefly during a switch — the reason CMOS logic burns almost no static power.

One Inverter

Mon, 01 Jan 0001 00:00:00 +0000

One Inverter#

The problem is small and extremely common: a design needs exactly one inverter — to flip an active-low signal to active-high, correct a polarity, or generate a complement — and nothing else. Dropping a 14-pin hex inverter to use one-sixth of it is wasteful on a modern board.

The Part#

Reach for a single-gate (“tiny logic”) inverter: the 74LVC1G04 in a tiny SOT-23-5 or smaller package, running at low voltage with 5 V-tolerant inputs. On an all-5 V board the classic 74HC04 hex inverter still works if the extra five gates can be spared or reused elsewhere. If the signal is also slow or noisy, use the Schmitt-trigger version (74LVC1G14 / 74HC14) and get debounce-grade edge cleaning in the same part.

Propagation Delay & Fan-Out

Mon, 01 Jan 0001 00:00:00 +0000

Propagation Delay & Fan-Out#

The first crack in the ideal picture is that a gate does not respond instantly. Propagation delay is the time between an input changing and the output following — a few nanoseconds for ordinary logic, but never zero. Every timing limit in a digital system traces back to this one fact.

Delay Accumulates Along a Path#

Delays add up along a chain of gates. A signal passing through five gates arrives roughly five gate-delays late, and the critical path — the slowest route from one register to the next — sets how fast the whole circuit can run. This is why a ripple counter and a ripple-carry adder slow down as they get wider: the carry has to propagate stage by stage, and nothing downstream is valid until it arrives. It is also why hazards and glitches exist at all — two paths of unequal delay reconverging produce a transient wrong value. Shortening the critical path, by using fewer levels of logic or faster carry schemes, is how a design is made to run faster.

Relays

Mon, 01 Jan 0001 00:00:00 +0000

Relays#

A relay is an electrically controlled switch: a coil, when energized, generates a magnetic field that pulls a movable armature, and that armature opens or closes a set of contacts. The essential feature is not the switching itself but the separation — the coil that does the controlling is electrically independent of the contacts being controlled. One circuit commands another.

That single property is the seed of all logic. A plain switch is thrown by a hand or a cam; a relay is thrown by another circuit’s output. Once a switch can be operated by the same kind of signal it produces, switches can be cascaded — the output of one drives the input of the next — and cascaded switches are exactly what a logic gate is.

Ripple Counters

Mon, 01 Jan 0001 00:00:00 +0000

Ripple Counters#

A ripple counter is the simplest way to count in hardware: a chain of toggle flip-flops in which each stage’s output clocks the next. The first stage toggles on the input clock, dividing it by two; its output clocks the second stage, dividing by two again; and so on. With n stages the chain counts from 0 to 2ⁿ−1 in binary and divides the input frequency by 2ⁿ — all from flip-flops and a wire, no logic gates and no software.

RTL

Mon, 01 Jan 0001 00:00:00 +0000

RTL#

Resistor-Transistor Logic was the first practical way to build logic gates inside an integrated circuit. Its name is its schematic: resistors at the inputs, a transistor doing the switching. It is obsolete now, but it is where the family tree starts, and every weakness of RTL is the reason the next family exists.

How It’s Built#

The basic RTL gate is a NOR. Each input drives the base of its own transistor through a resistor; all the transistors share a single collector resistor to the supply. If any input is high, its transistor conducts and pulls the shared output low — low-when-any-input-is-high is exactly NOR. Adding transistors in parallel adds inputs; that is the entire trick.

Shift Registers

Mon, 01 Jan 0001 00:00:00 +0000

Shift Registers#

A shift register is a row of flip-flops wired so that each one’s output feeds the next one’s input. On every clock edge the whole row shifts its contents one position along. Where a plain register holds a word still, a shift register makes it move — which is the basis for nearly every way hardware moves data on a small number of wires.

Serial and Parallel, in Four Combinations#

The value of a shift register is converting between serial and parallel form, and parts are named for how data enters and leaves:

SR Latch

Mon, 01 Jan 0001 00:00:00 +0000

SR Latch#

The SR (set-reset) latch is the simplest memory element, and it is the seed from which every latch, flip-flop, and register grows. Cross-couple two gates so that each one’s output feeds back into the other’s input, and the pair becomes bistable: it has two stable states and will rest in whichever one it was last driven into, holding that state after the driving input is removed. That feedback loop is what “remembering” means in hardware.

Truth Tables

Mon, 01 Jan 0001 00:00:00 +0000

Truth Tables#

A truth table is the complete, unambiguous specification of a combinational function: every possible input combination on the left, the output it must produce on the right. It says what a function does without saying anything about how it is built, which makes it the natural starting point for every design and the common ground between a specification and a circuit.

Complete, but It Scales Badly#

For n inputs there are 2ⁿ combinations, so a truth table has 2ⁿ rows. That is fine for the two- and three-input gates whose behavior is a small truth table, but it grows explosively: four inputs give 16 rows, eight give 256, and twenty give over a million. Completeness is the strength and the weakness — nothing is left unspecified, but the table is unusable as a design tool much past a handful of variables. That is exactly why the rest of this subsection exists: Boolean algebra and canonical forms compress the table into an expression, and Karnaugh maps reorganize it to be simplified by eye.

What Is a State Machine?

Mon, 01 Jan 0001 00:00:00 +0000

What Is a State Machine?#

A finite state machine is the most general form a sequential circuit can take. It is defined by three things: a finite set of states, a rule for choosing the next state from the current state and the inputs, and a rule for producing outputs. Anything that has to remember where it is and act on what happens next — a controller, a protocol handler, a vending machine — is a state machine.

Analog Switches

Mon, 01 Jan 0001 00:00:00 +0000

Analog Switches#

An analog switch lets a digital signal turn an analog one on and off. Where a logic gate can only handle clean highs and lows, an analog switch passes whatever voltage sits on it — an audio signal, a sensor output, a reference — while a logic-level control decides whether the path is open or closed. It is the fundamental primitive for routing analog signals under digital control.

AND

Mon, 01 Jan 0001 00:00:00 +0000

AND#

The AND gate outputs high only when all of its inputs are high. It is the “every condition met” gate: the output asserts precisely when nothing is missing.

A	B	A AND B
0	0	0
0	1	0
1	0	0
1	1	1

The physical picture is two switches in series: current reaches the output only when both are closed, which is exactly the behavior first built from relay contacts in series.

Boolean Algebra

Mon, 01 Jan 0001 00:00:00 +0000

Boolean Algebra#

Boolean algebra is the algebra of two-valued logic: variables that are only ever 0 or 1, combined with three operations — AND (·), OR (+), and NOT (′). It is the lever between a truth table and a circuit, because it lets a logic expression be manipulated and simplified on paper before a single gate is committed. Fewer terms mean fewer gates, fewer levels of logic, less delay, and less power.

Bus Transceivers

Mon, 01 Jan 0001 00:00:00 +0000

Bus Transceivers#

A bus transceiver is a bidirectional buffer with direction control — the part that lets a device drive a shared bus, receive from it, and get out of the way when it is not its turn. It exists because a bus is a set of wires many devices share, and sharing wires safely is harder than it looks.

The Problem of a Shared Bus#

On a bus, several devices connect to the same lines, but only one may drive them at any instant. If two devices drive the same wire to opposite levels, they fight — a low-impedance path from supply to ground that corrupts the data and can damage the drivers. This is bus contention, and avoiding it is the whole discipline of bus design: every device must present a three-state output that can go high-impedance (electrically disconnected) whenever it is not the active driver.

D Latch

Mon, 01 Jan 0001 00:00:00 +0000

D Latch#

The D latch fixes the two awkward things about the raw SR latch: its forbidden state, and its lack of any control over when it listens. It does this by adding a single data input D and an enable, arranged so that set and reset can never be asserted at the same time.

Transparent When Enabled#

Steering logic drives the internal set/reset from D and its complement, gated by the enable. The result is simple to state:

Debounce

Mon, 01 Jan 0001 00:00:00 +0000

Debounce#

A mechanical switch or button does not make one clean transition. Its contacts — like the relay contacts that first exposed the problem — bounce for a few milliseconds on every closure, producing a burst of edges that a fast logic input or an interrupt reads as many presses.

The Part#

The classic answer is a 74HC14 hex Schmitt-trigger inverter (or the single-gate 74LVC1G14) with a small RC filter on its input. The resistor and capacitor slow the signal so the bounce is smeared into a gentle ramp; the Schmitt input’s hysteresis then turns that ramp into exactly one clean edge, ignoring the wobble in between.

DTL

Mon, 01 Jan 0001 00:00:00 +0000

DTL#

Diode-Transistor Logic answered RTL’s weaknesses by changing what does the logic at the input: diodes instead of resistors. It is also obsolete, but it is the most instructive stop in the lineage, because understanding DTL is understanding exactly what problem TTL then solved.

How It’s Built#

DTL splits the work in two. A network of diodes at the input performs the combinational logic — several diodes into a common node form an AND — and a transistor stage behind it inverts and restores the signal to a clean level. Diode-AND followed by transistor-inversion is a NAND, the characteristic DTL gate.

Encoder

Mon, 01 Jan 0001 00:00:00 +0000

Encoder#

An encoder is the reverse of a decoder: it takes 2ⁿ inputs, one of them active, and produces the n-bit binary code that names which one. Eight input lines become a 3-bit number, sixteen become a 4-bit number. Where a decoder expands a code into one-hot, an encoder compresses one-hot back into a code.

The Problem of More Than One#

A plain encoder assumes exactly one input is active. If two are high at once, the naïve output is meaningless — it is neither input’s code. Real inputs do not cooperate, so the useful part is the priority encoder: when several inputs are active, it outputs the code of the highest-priority one and ignores the rest, usually flagging separately whether any input was active at all. The standard parts are the 74148 (8-to-3 priority) and 74147 (10-line-to-4-line BCD priority).

Moore vs. Mealy

Mon, 01 Jan 0001 00:00:00 +0000

Moore vs. Mealy#

The two classic styles of state machine differ in one respect: what the outputs depend on. It is the first design decision after deciding a machine is needed, and it trades response speed against clean, predictable timing.

The Distinction#

A Moore machine’s outputs depend only on the current state. The output logic looks at the state register and nothing else, so outputs change only after a clock edge moves the machine to a new state.
A Mealy machine’s outputs depend on the current state and the current inputs together. An input change can ripple straight to an output within the same state, without waiting for a clock edge.

The Trade-off#

Because a Moore output is a function of the registered state alone, it is clean and glitch-free — it changes synchronously, once per transition, and never twitches in response to a noisy input. The cost is a step of latency (the machine must clock into a new state before the output reflects an input) and sometimes more states, since distinctions that a Mealy machine draws with inputs must become separate states.

PLDs & CPLDs

Mon, 01 Jan 0001 00:00:00 +0000

PLDs & CPLDs#

Programmable logic devices are the step between fixed-function chips and the FPGA: user-defined logic without custom silicon. They exist to answer a specific frustration — a board covered in 74xx glue that has to be redesigned every time the logic changes — by putting that glue into a single part whose function is programmed, not wired.

From PAL to GAL to CPLD#

The original PLDs implemented logic as a programmable sum-of-products array: a grid of AND terms feeding OR terms, with fuses (PAL) or reprogrammable cells (GAL) selecting which connections are made. Because any Boolean function can be written in sum-of-products form, that one structure can implement a wide range of combinational logic — and with a flip-flop on each output, small state machines too. A single GAL could swallow a fistful of gates, decoders, and latches.

Setup & Hold Time

Mon, 01 Jan 0001 00:00:00 +0000

Setup & Hold Time#

A flip-flop captures its data input at the clock edge, but only if that data is stable in a narrow window around the edge. Setup time is how long the data must be steady before the edge; hold time is how long it must remain steady after. Meet both and the flip-flop captures a clean value; violate either and it can go metastable. These two numbers are the foundation on which all synchronous timing rests.

Subtractors

Mon, 01 Jan 0001 00:00:00 +0000

Subtractors#

Hardware rarely builds a dedicated subtractor, because it does not need one. Subtraction is addition of a negative number, and in two’s-complement arithmetic negating a number is nearly free — so the same adder that adds also subtracts, with a trivial change to its inputs.

Subtraction Is Addition in Disguise#

In two’s complement, a number is negated by inverting all its bits and adding 1. Therefore:

Synchronous Counters

Mon, 01 Jan 0001 00:00:00 +0000

Synchronous Counters#

A synchronous counter fixes the ripple counter’s central flaw by clocking every flip-flop from the same clock at the same time. There is no ripple: on each edge all stages that need to change do so together, so the count is valid all at once and the counter runs as fast as a single stage allows.

Knowing When to Toggle#

If every flip-flop shares the clock, each one needs to be told in advance whether to flip on the coming edge. That is the job of a little combinational logic: a stage toggles only when all the stages below it are already 1. Stage 0 toggles every edge; stage 1 toggles when bit 0 is 1; stage 2 toggles when bits 0 and 1 are both 1 — a chain of AND gates feeding each flip-flop’s toggle enable. The flip-flops still all fire on the same edge; the logic just decides which ones act.

Vacuum Tubes

Mon, 01 Jan 0001 00:00:00 +0000

Vacuum Tubes#

The vacuum tube was the first device to switch electronically — with no moving parts. Where a relay throws a metal armature to make or break a circuit, a tube controls a stream of electrons flying through a vacuum. Nothing mechanical moves, so switching happens at the speed of electron flow rather than the speed of a spring. That single change took switching from milliseconds to microseconds, and it is what made genuinely fast computation possible.

Buffers

Mon, 01 Jan 0001 00:00:00 +0000

Buffers#

A buffer is a gate that computes nothing — its output simply equals its input — yet it is one of the most useful parts in the toolbox. What a buffer provides is not logic but electrical help: drive, isolation, and, in its three-state form, the ability to disconnect.

The Gate That Does Nothing, Usefully#

A non-inverting buffer is, at heart, two inverters in series — the double inversion cancels, leaving the logic value unchanged but the signal freshly restored and able to drive a much heavier load than the original could. That buys three things:

Clocks & Distribution

Mon, 01 Jan 0001 00:00:00 +0000

Clocks & Distribution#

The clock is the heartbeat that keeps a synchronous system in step: every flip-flop updates on its edge, so the whole machine advances together. That only works if a clean edge reaches every flip-flop at very nearly the same instant — which is harder than it sounds, and where a surprising amount of real-world timing trouble lives.

Where Clocks Come From#

A clock starts at an oscillator. A crystal oscillator gives an accurate, stable frequency and is the reference for anything that must keep real time or talk to the outside world. Cheaper RC or ring oscillators are built from an inverter and a delay, trading precision for cost — the Schmitt-trigger relaxation oscillator is the simplest example. A PLL multiplies or divides a reference to synthesize the several frequencies a modern chip needs, and simple frequency dividers derive slower clocks from a fast one.

D Flip-Flop

Mon, 01 Jan 0001 00:00:00 +0000

D Flip-Flop#

The D flip-flop is the workhorse of sequential logic — the element behind essentially every register, counter, shift register, state machine, and pipeline stage in a modern design. It stores one bit, and it captures that bit at a single, well-defined instant: the clock edge.

Edge-Triggered, Not Level-Sensitive#

This is the one distinction that matters. A D latch is transparent — its output follows D the whole time it is enabled. A D flip-flop instead samples D only at the rising (or falling) edge of the clock and holds that value for the entire cycle until the next edge, ignoring anything D does in between.

De Morgan's Theorems

Mon, 01 Jan 0001 00:00:00 +0000

De Morgan’s Theorems#

De Morgan’s theorems are the two most-used identities in all of digital logic. They describe what happens when the output of an AND or an OR is inverted:

$$ (A \cdot B)’ = A’ + B’ $$

$$ (A + B)’ = A’ \cdot B’ $$

In words: inverting the output of a gate is the same as swapping the gate type (AND ↔ OR) and inverting every input. The theorems extend to any number of inputs — the complement of a whole product is the sum of the complemented terms, and vice versa.

FPGAs

Mon, 01 Jan 0001 00:00:00 +0000

FPGAs#

A Field-Programmable Gate Array is the building blocks of this book made configurable: a fabric of logic and flip-flops whose function is defined after manufacture by loading a configuration. Where a microcontroller turns logic into a sequential program, an FPGA turns it into actual parallel hardware — every part of the design runs at once, the way discrete logic always did.

A Fabric of Lookup Tables and Flip-Flops#

The fabric is made of many small configurable blocks, each holding a lookup table (LUT) and a flip-flop, tied together by a mesh of programmable interconnect and surrounded by configurable I/O.

Frequency Dividers

Mon, 01 Jan 0001 00:00:00 +0000

Frequency Dividers#

A frequency divider produces a slower clock from a faster one, and a counter is already a frequency divider — the two are the same circuit viewed two ways. Every toggle flip-flop stage halves the frequency, so an n-stage counter divides its input by 2ⁿ while it counts. Deriving usable clocks this way is one of the most common jobs a counter does.

Dividing by Two, by 2ⁿ, and by N#

Dividing by a power of two is free: tap the output of the right stage of a binary counter. Stage 0 gives ÷2, stage 3 gives ÷16, and so on.

Magnitude Comparators

Mon, 01 Jan 0001 00:00:00 +0000

Magnitude Comparators#

A magnitude comparator decides the relationship between two binary numbers — whether A equals B, A is greater, or A is less. It answers in logic what a subtraction answers in arithmetic, and it is a distinct, common building block wherever hardware has to make a decision about a value.

Note: this is the digital comparator, comparing multi-bit numbers. It shares its name with the analog voltage comparator in Analog Helpers, which compares two continuous voltages and outputs a single bit — a different device for a different job.

More Outputs

Mon, 01 Jan 0001 00:00:00 +0000

More Outputs#

A microcontroller or FPGA has run out of pins, but the design still needs to drive many things — a bank of LEDs, seven-segment digits, relays, or status lines. The trick is to trade a few pins and a little time for as many outputs as needed.

The Part#

The workhorse is the 74HC595, an 8-bit serial-in, parallel-out shift register with a latched output. Three signals — data, shift clock, and latch — feed eight bits in serially, and the latch then presents all eight at the outputs at once (so they change cleanly together rather than rippling). Its serial-output pin feeds the next ‘595’s input, so devices daisy-chain: three pins can drive 8, 16, 24, or more outputs, limited mainly by how long the shifting takes.

Multiplexer

Mon, 01 Jan 0001 00:00:00 +0000

Multiplexer#

A multiplexer (mux) selects one of many inputs and passes it to a single output, chosen by a set of select lines. With n select lines it picks among 2ⁿ inputs — an 8-to-1 mux needs three. It is the fundamental data router: many sources, one destination, and a control that decides which source gets through.

The standard parts are the 74151 (8-to-1), 74153 (dual 4-to-1), and 74157 (quad 2-to-1). Internally a mux is a decoder on the select lines enabling one input path, all OR-ed together — select, gate, combine.

OR

Mon, 01 Jan 0001 00:00:00 +0000

OR#

The OR gate outputs high when any of its inputs is high. It is the “at least one condition met” gate, and the natural counterpart to AND.

A	B	A OR B
0	0	0
0	1	1
1	0	1
1	1	1

The physical picture is two switches in parallel: current reaches the output if either one is closed — the behavior built from relay contacts in parallel.

Sample & Hold

Mon, 01 Jan 0001 00:00:00 +0000

Sample & Hold#

A sample-and-hold captures an analog voltage at a chosen instant and holds it steady long enough to be measured. It exists because measurement takes time: an analog-to-digital converter needs its input to stay constant while it works out the digital value, and a signal that moves during the conversion produces a wrong reading. Sample-and-hold freezes the signal at a defined moment so the converter has something still to look at.

State Diagrams

Mon, 01 Jan 0001 00:00:00 +0000

State Diagrams#

A state diagram is how a state machine is designed before any gates exist. States are drawn as bubbles and transitions as arrows labeled with the input condition that causes them. It is the specification the machine is reasoned about — the logic is derived from the diagram, not the other way around.

A Worked Example#

The canonical example is a turnstile. It has two states — Locked and Unlocked — and two inputs: inserting a coin and pushing the arm.

Transistors

Mon, 01 Jan 0001 00:00:00 +0000

Transistors#

The transistor is the solid-state switch — the semiconductor successor to the vacuum tube’s triode, doing the same job with no heater, no vacuum, and nothing moving. A small signal on one terminal controls a much larger current between the other two, exactly as the tube’s grid controlled its plate current, but now the control happens inside a sliver of doped silicon. Demonstrated at Bell Labs in 1947, it is the device every logic family and every chip in the rest of this notebook is ultimately built from. It is also the hinge of the whole story: the last switch small and cheap enough to hold in the hand, and the first one that could be replicated by the million on a single piece of silicon.

TTL

Mon, 01 Jan 0001 00:00:00 +0000

TTL#

Transistor-Transistor Logic was the family that made integrated logic ubiquitous. For roughly two decades it was simply what “a logic chip” meant, and although CMOS has replaced it in almost every new design, TTL’s conventions — its part numbers and its voltage levels — are so deeply embedded that they still govern logic built today.

How It’s Built#

TTL took DTL and replaced its two weak spots. The string of input diodes became a single multi-emitter transistor: each emitter is an input, and the transistor actively sweeps charge out of the following stage, switching far faster than passive diodes could. The passive pull-up became a totem-pole output — a stacked pair of transistors that actively drives the output both high and low, giving fast edges and real drive strength. The signature gate is the 7400 quad two-input NAND.

Canonical Forms (SOP & POS)

Mon, 01 Jan 0001 00:00:00 +0000

Canonical Forms (SOP & POS)#

A canonical form is a systematic, mechanical way to write down a function straight from its truth table — no cleverness required. There are two, and they are duals of each other: sum of products, built from the rows where the output is 1, and product of sums, built from the rows where it is 0.

Sum of Products (from the 1s)#

For each row where the output is 1, write a minterm: the AND of every input variable, taken true where the variable is 1 and complemented where it is 0. OR all those minterms together and the result is the sum-of-products (SOP) form — it is 1 for exactly the input combinations that should give 1, and nothing else. For a function that is 1 on rows 3 and 5 of three variables, F = A′BC + AB′C, often written compactly as Σm(3, 5).

CMOS

Mon, 01 Jan 0001 00:00:00 +0000

CMOS#

Complementary Metal-Oxide-Semiconductor logic is the milestone the whole lineage was building toward. Every other family on this list is either an ancestor of CMOS or a variety of it, and every integrated circuit in a modern device — processor, memory, FPGA, microcontroller — is CMOS underneath. It won on the one axis that ultimately mattered most: power.

How It’s Built#

A CMOS gate uses two complementary networks between the output and the rails: a PMOS network that can pull the output high and an NMOS network that can pull it low, arranged so that in any stable input state exactly one network conducts. Because there is never a path from supply to ground in a settled state, a CMOS gate draws essentially no static current — it dissipates power only briefly while switching, charging and discharging capacitance.

Demultiplexer

Mon, 01 Jan 0001 00:00:00 +0000

Demultiplexer#

A demultiplexer (demux) is the reverse of a multiplexer: it takes a single input and routes it to one of many outputs, chosen by the select lines. One source, many destinations, and a control that decides which destination receives the signal while the others stay idle.

The Same Hardware as a Decoder#

A demux is not a distinct circuit — it is a decoder with its enable input used as the data input. The decoder already activates exactly the one output named by the select lines; feed data into its enable and that selected output follows the data instead of simply going active. This is why a part like the 74138 is sold as a “decoder/demultiplexer”: the two functions are one piece of silicon addressed two ways. When the input is held permanently active it is a decoder; when the input carries data it is a demux.

HDL Concepts

Mon, 01 Jan 0001 00:00:00 +0000

HDL Concepts#

A hardware description language — Verilog or VHDL — is how logic is actually specified once there is too much of it to draw. Nobody schematics a million gates; instead they describe the intended behavior in an HDL, and a synthesis tool turns that description into real gates and flip-flops, whether for an FPGA’s fabric or an ASIC’s cells.

It Describes Hardware, It Does Not Run#

The single most important idea — and the one that trips up newcomers from software — is that an HDL describes hardware that all exists at once; it is not a program that executes line by line. When a Verilog file says one signal is the AND of two others and, elsewhere, that a third is the OR of two more, both pieces of logic are built and both operate concurrently, forever. There is no “first this, then that.” Order of appearance is irrelevant; everything is simultaneous, because it is describing wires and gates, not instructions.

JK Flip-Flop

Mon, 01 Jan 0001 00:00:00 +0000

JK Flip-Flop#

The JK flip-flop is the SR latch’s clocked, well-behaved descendant — and, for the discrete-logic era, its most versatile one. It takes SR’s set and reset inputs (here called J and K) but replaces the forbidden “both asserted” combination with something useful: toggle.

J	K	Q (next)
0	0	Q — hold
1	0	1 — set
0	1	0 — reset
1	1	Q̄ — toggle

With J and K both high, each clock edge flips the output. That closes the one gap SR left open and makes a single flip-flop able to hold, set, reset, or toggle depending only on how its inputs are wired.

Metastability & Synchronizers

Mon, 01 Jan 0001 00:00:00 +0000

Metastability & Synchronizers#

When a flip-flop’s setup or hold window is violated — its data changes right at the clock edge — it may not cleanly capture a 0 or a 1. Instead it can enter metastability: an unstable in-between condition where the output hovers at an invalid level, or oscillates, before eventually settling to one value or the other. This is the sharpest way the digital abstraction breaks, and it cannot be designed away — only managed.

More Inputs

Mon, 01 Jan 0001 00:00:00 +0000

More Inputs#

The mirror of the output problem: a design needs to read more switches, buttons, or digital sensors than there are pins to spare. The same shift-register trick works in reverse — sample many inputs, then clock them out over a few wires.

The Part#

The go-to is the 74HC165, an 8-bit parallel-in, serial-out shift register. A load pulse captures all eight inputs at once into the register; the controller then clocks those bits out serially on a single data line. Like the 74HC595 it daisy-chains — each ‘165’s serial output feeds the next’s input — so three pins can read 8, 16, or more inputs. The ‘595 for outputs and the ‘165 for inputs are the standard complementary pair.

NAND

Mon, 01 Jan 0001 00:00:00 +0000

NAND#

NAND is AND followed by inversion: the output is low only when all inputs are high, and high otherwise. That small change — putting a bubble on the AND — turns out to be one of the most important facts in digital logic, because NAND can build everything else.

A	B	A NAND B
0	0	1
0	1	1
1	0	1
1	1	0

Why NAND Is Universal#

NAND is functionally complete: any Boolean function whatsoever can be built from NAND gates alone. An inverter is a NAND with its inputs tied together; an AND is a NAND followed by that inverter; an OR is a NAND with both inputs inverted — which, by De Morgan’s theorems, a NAND already is when its inputs are read as inverted. From those, every other gate and every larger function follows. A designer given nothing but NAND gates is not missing anything.

Op-Amps (Briefly)

Mon, 01 Jan 0001 00:00:00 +0000

Op-Amps (Briefly)#

The operational amplifier is the general-purpose gain block of analog electronics, and it earns a place in a digital notebook only for what it does at the boundary: conditioning a real-world signal so the digital side can use it. This page stays deliberately brief — the full treatment of op-amps belongs to the EE Notebook’s analog sections.

What It Is#

An op-amp is a high-gain differential amplifier. On its own that open-loop gain is unusably large, but wrapped in feedback it becomes precise and versatile: amplify, attenuate, buffer, filter, sum, or offset a signal, with the behavior set by a handful of external resistors and capacitors. It is the analog equivalent of a Swiss-army knife, and a comparator is essentially the same device run without feedback so its output swings fully to the rails.

Parity & Error Detection

Mon, 01 Jan 0001 00:00:00 +0000

Parity & Error Detection#

Parity is the cheapest integrity check in digital logic: a single extra bit that reveals whether data has been corrupted in the simplest way. It costs almost nothing to compute, which is exactly why it has been used everywhere from memory to serial links for decades.

One XOR Tree#

The parity of a group of bits is whether the count of 1s among them is odd — and that is precisely what an XOR of all the bits computes. A parity generator is therefore just an XOR tree across the data. A parity bit is appended so that the total number of 1s is always even (even parity) or always odd (odd parity), as agreed in advance.

Ring & Johnson Counters

Mon, 01 Jan 0001 00:00:00 +0000

Ring & Johnson Counters#

Ring and Johnson counters count differently from a binary counter: instead of incrementing a number, they circulate a pattern around a shift register. They trade code efficiency for something valuable — outputs that are already decoded and free of glitches.

Ring Counter#

A ring counter is a shift register with its last output fed straight back to its first input. Seed it with a single 1 and that one bit walks around the loop: 1000 → 0100 → 0010 → 0001 → 1000. With N flip-flops it has N states, and exactly one output is active at a time — a one-hot sequence. Because each output is a decoded state, no decoding logic is needed and there are none of the ripple-counter decoding glitches: the outputs are already clean, one-per-step control signals. That makes ring counters ideal for sequencers, stepper-motor phase drives, and LED chasers.

State Encoding

Mon, 01 Jan 0001 00:00:00 +0000

State Encoding#

Once a state machine’s behavior is captured, each state has to be assigned a bit pattern in the state register. The behavior is identical whatever the assignment, but the encoding strongly affects how much logic the machine costs, how fast it runs, and how safely it fails — so it is a real design choice, not a formality.

Three Common Schemes#

Binary (sequential) — number the states 0, 1, 2, … and store the number in ⌈log₂ N⌉ flip-flops. This uses the fewest flip-flops, which mattered when flip-flops were expensive discrete parts. The cost is more complex next-state and output logic, and several bits can change on one transition — a source of decoding glitches.
Gray code — order the state codes so that adjacent states differ by a single bit. Only one flip-flop changes per step, which reduces simultaneous switching and makes decoded outputs cleaner. It is most useful for machines that march through states in order, and for values that cross clock domains.
One-hot — give each state its own flip-flop, with exactly one set at a time. It spends the most flip-flops (N of them for N states) but makes the next-state and output logic trivial and fast: “am I in state X” is just one flip-flop’s output, with no decoding. A one-hot machine is essentially a ring counter following the state diagram.

Choosing One#

The trade is flip-flops against logic. In the discrete and early-integrated eras, flip-flops were the scarce resource, so binary encoding dominated. In an FPGA, flip-flops come essentially free with every logic block while wide combinational logic is what’s precious — so one-hot is frequently the default, trading spare flip-flops for smaller, faster logic and glitch-free decoding.

Why Integrated Circuits Happened

Mon, 01 Jan 0001 00:00:00 +0000

Why Integrated Circuits Happened#

The transistor made a single switch cheap, small, and reliable. That solved the device problem — but it exposed a new one. As designs grew from dozens of transistors to thousands, the limiting factor stopped being the transistors and became the wiring between them. The integrated circuit exists to solve that second problem, and understanding which problem it solved is the key to why every later chapter looks the way it does.

ALU

Mon, 01 Jan 0001 00:00:00 +0000

ALU#

The Arithmetic Logic Unit is where the building blocks converge. It is a single combinational block that performs a selected operation — add, subtract, AND, OR, XOR, compare, shift — on its two operands, with function-select inputs choosing which. It is the computational core of a processor’s datapath, and it is assembled almost entirely from the primitives covered elsewhere in this section.

What It Combines#

An ALU is less an invention than an arrangement:

ASICs

Mon, 01 Jan 0001 00:00:00 +0000

ASICs#

An Application-Specific Integrated Circuit is custom silicon: the logic of a design fixed permanently into a chip made for one purpose. It is the building blocks of this book laid out in silicon at scale — millions or billions of gates and flip-flops, placed once and never changed.

The Primitives, Fixed in Silicon#

Most ASICs are built from a standard-cell library: a catalog of pre-designed, pre-characterized layouts for each primitive — a NAND cell, a NOR cell, a D flip-flop cell, a full-adder cell, and so on. That library is nothing more than the gates of Part II rendered as physical geometry. A designer writes the logic in an HDL, synthesis maps it onto those cells, and place-and-route tools arrange and wire millions of them across the die. (Gate arrays and full-custom design are the other, less common points on the spectrum, trading flexibility for effort.)

Clock Domain Crossing

Mon, 01 Jan 0001 00:00:00 +0000

Clock Domain Crossing#

A modern chip does not run on one clock. A processor core, a memory interface, a radio, and a USB port each have their own, and signals constantly have to pass between them. Whenever a signal generated in one clock domain is sampled by another whose clock is unrelated, it is a clock domain crossing (CDC) — and it is where metastability stops being a curiosity and becomes a design discipline.

HC / HCT Families

Mon, 01 Jan 0001 00:00:00 +0000

HC / HCT Families#

The 74HC and 74HCT families are where CMOS became the practical default for board-level logic. They pair CMOS power consumption with speed comparable to the popular 74LS TTL of their day, wrapped in the familiar 74xx part numbers — which is why, for a great deal of discrete digital design, “HC” is simply the logic reached for first.

High-Speed CMOS#

74HC (“High-speed CMOS”) is silicon-gate CMOS built to be fast enough to replace LS-TTL while keeping CMOS’s near-zero static power, its wide 2–6 V supply range, and its high, rail-to-rail noise margin (thresholds near half the supply). Functionally it carries the entire 74xx catalog forward: a 74HC00 is the CMOS quad NAND, a 74HC595 the CMOS shift register, and so on.

Karnaugh Maps

Mon, 01 Jan 0001 00:00:00 +0000

Karnaugh Maps#

A Karnaugh map is a truth table rearranged so that simplification becomes something the eye can do. The rows and columns are ordered in Gray code — each cell differs from its neighbors by exactly one variable — so that physically adjacent 1s can always be combined into a simpler term. It turns the algebra of minimization into pattern-spotting.

Reading the Grid#

Here is a three-variable function, F(A, B, C), with the columns in Gray order (00, 01, 11, 10):

NOR

Mon, 01 Jan 0001 00:00:00 +0000

NOR#

NOR is OR followed by inversion: the output is high only when all inputs are low, and low if any input is high. Like NAND, it is a universal gate — and it holds a special place in the history of the field.

A	B	A NOR B
0	0	1
0	1	0
1	0	0
1	1	0

Universal, and the Mirror of NAND#

NOR is functionally complete: an inverter is a NOR with its inputs tied together, and every other gate follows. It is the De Morgan dual of NAND — a NOR behaves as an AND with inverted inputs — so a design can be built entirely from NOR just as it can be built entirely from NAND. In CMOS it is equally native and cheap: four transistors for a two-input gate, where a true OR needs six.

Sequencers

Mon, 01 Jan 0001 00:00:00 +0000

Sequencers#

A sequencer is a state machine in its most restricted, most common form: one that steps through a fixed sequence of states, mostly marching forward rather than branching on inputs. Where a general FSM asks “given where I am and what just happened, where do I go?”, a sequencer mostly just asks “what is the next step?” That narrower job has simple, efficient realizations.

How They’re Built#

Counter plus decoder — a synchronous counter advances through binary states and a decoder turns the current count into one active “step” line. Compact, and the count is also directly available.
Ring or Johnson counter — a ring counter is the simplest sequencer of all: the single circulating one-hot bit is the current step, already decoded and glitch-free, with no separate decoder needed.
A small FSM — when a few input-dependent decisions are needed (wait here until ready, skip a step under some condition), a general state machine handles the branches the pure counter forms cannot.

Where They’re Used#

Sequencers run the parts of a system that must happen in a fixed order: multi-phase clock generation, memory and bus access cycles, stepper-motor phase drive, display and keypad scanning, and pattern or waveform generation. Their most consequential use is the control unit of a processor — a microsequencer that steps an address counter through a ROM whose contents are the control signals for each step (microcode) and the address of the next step. That is how a great many CPUs turn an instruction into an ordered series of register-transfer operations: a sequencer, a memory, and the datapath registers it steers. The counting family’s pattern circulators and the state-machine family’s controllers meet exactly here.

SSI, MSI, LSI & VLSI

Mon, 01 Jan 0001 00:00:00 +0000

SSI, MSI, LSI & VLSI#

Once whole circuits could be fabricated at once, the only open question was how many devices to put on a single die. The answer grew by orders of magnitude over two decades, and the industry named the rungs of that climb: small-, medium-, large-, and very-large-scale integration. The names are worth knowing not as trivia but because each rung sold a different level of abstraction as a product — and that progression is exactly how the rest of this notebook is organized.

Switch Analog Signals

Mon, 01 Jan 0001 00:00:00 +0000

Switch Analog Signals#

A logic gate cannot pass an analog signal, and a relay is bulky and slow for routing a small voltage. The need here is to steer an analog signal — an audio line, a sensor voltage, a reference — on and off, or from one path to another, under digital control.

The Part#

The classic answer is the 4066, a quad bilateral (analog) switch. Each switch is a CMOS transmission gate — an NMOS and a PMOS transistor in parallel — that, when its control input is high, conducts in either direction and passes whatever analog voltage sits between the supply rails. When the control is low, the path is open. It is a genuine switch for signals, controlled by a logic level.

T Flip-Flop

Mon, 01 Jan 0001 00:00:00 +0000

T Flip-Flop#

The T (toggle) flip-flop does one thing: when its T input is high, it flips state on every clock edge; when T is low, it holds. That single behavior makes it the building block of counters and frequency dividers.

T	Q (next)
0	Q — hold
1	Q̄ — toggle

Divide by Two#

A flip-flop that toggles on each clock edge produces an output that changes half as often as its clock — a divide-by-two. Feed that output into the clock of a second toggle stage and it divides by two again; chain n stages and the result counts in binary and divides the input frequency by 2ⁿ. That is precisely how a ripple counter works, and why the T flip-flop lives at the root of the counting primitives.

Hazards & Glitches

Mon, 01 Jan 0001 00:00:00 +0000

Hazards & Glitches#

A truth table describes what a function settles to, not the momentary values it passes through on the way. Real gates take time to switch, and different signal paths through a circuit take different amounts of time — so when an input changes, the output can briefly show a wrong value before settling to the right one. That transient is a glitch, and the circuit property that permits it is a hazard. The logic is correct; the timing is not.

LVC / AHC

Mon, 01 Jan 0001 00:00:00 +0000

LVC / AHC#

As supply voltages fell — 5 V giving way to 3.3 V, then 1.8 V and below, for both power savings and speed — logic families followed them down. LVC, AHC, and their many siblings are today’s discrete logic: the parts actually specified in current designs, where HC/HCT is increasingly the legacy 5 V choice.

Today’s Low-Voltage CMOS#

These are all CMOS, refined for lower voltages, higher speed, and mixed-voltage systems:

One of Eight Sensors

Mon, 01 Jan 0001 00:00:00 +0000

One of Eight Sensors#

A design has one ADC input but eight analog sensors to read (or one signal path that must select among eight sources). Rather than eight converters, route each sensor to the single ADC in turn.

The Part#

The standard part is the 4051, an 8-channel analog multiplexer/demultiplexer. Three address lines select which of the eight channels connects to the common pin, and because it is built from transmission gates it passes analog voltages in either direction — so the same part can gather eight inputs to one ADC or fan one source out to eight destinations. Its relatives cover other groupings: the 4052 is a dual 4-channel mux, the 4053 a triple 2-channel. The 74HC4051 is the faster high-speed-CMOS version.

Registers

Mon, 01 Jan 0001 00:00:00 +0000

Registers#

A register is simply a row of D flip-flops sharing one clock, storing an N-bit word instead of a single bit. Where a flip-flop remembers a bit, a register remembers a number — and that makes it the basic unit of storage in any datapath.

A Word, Captured on a Clock#

Present a word at the register’s inputs, pulse the clock, and all N bits are captured together and held until the next clock — the same edge-triggered capture as a single flip-flop, widened. Because every bit latches on the same edge, the stored word is always internally consistent; there is no moment where half the bits are old and half are new. The classic octal parts are the 74HC574 and 74HC377 (eight D flip-flops with a shared clock, the latter with a load enable).

SoCs

Mon, 01 Jan 0001 00:00:00 +0000

SoCs#

A System on a Chip is integration taken to its conclusion: not just logic, and not just a processor, but a whole system on one die. Where a microcontroller put a CPU, memory, and simple peripherals together, an SoC adds everything else a product needs — multiple CPU cores, a GPU, a neural accelerator, memory controllers, high-speed I/O, radios, image and signal processors — onto a single piece of silicon.

XOR

Mon, 01 Jan 0001 00:00:00 +0000

XOR#

The exclusive-OR gate outputs high when its inputs differ and low when they match. Where OR asks “is any input high?”, XOR asks “is exactly an odd number of inputs high?” — for two inputs, “are they different?”

A	B	A XOR B
0	0	0
0	1	1
1	0	1
1	1	0

The Difference Detector#

XOR is fundamentally a difference detector, and two identities make it far more useful than that description suggests:

Level Shifting

Mon, 01 Jan 0001 00:00:00 +0000

Level Shifting#

Modern boards are rarely a single voltage. A 3.3 V microcontroller must talk to a 5 V sensor, a 1.8 V memory, or an I²C bus shared across domains, and connecting mismatched levels directly either fails to register a logic high or over-volts an input. Level shifting moves a signal safely from one voltage domain to another — and the right part depends entirely on the direction and the drive type.

Tiny Logic (74LVC1Gxx)

Mon, 01 Jan 0001 00:00:00 +0000

Tiny Logic (74LVC1Gxx)#

Tiny logic is the endpoint of discrete-logic miniaturization: one gate per package. Where the classic 7400 put four NAND gates in a 14-pin package, a part like the 74LVC1G00 is a single two-input NAND in a five-pin package smaller than a grain of rice. It is the most modern link in this chapter, and it exists because of what happened to logic everywhere else in the notebook.

XNOR

Mon, 01 Jan 0001 00:00:00 +0000

XNOR#

XNOR is the complement of XOR: its output is high when its inputs match and low when they differ. If XOR is the difference detector, XNOR is the equality detector.

A	B	A XNOR B
0	0	1
0	1	0
1	0	0
1	1	1

Equality in One Gate#

XNOR answers “are these two bits the same?” directly — a single gate that is high precisely when A equals B. Because it is XOR inverted, it shares XOR’s cost and its complementary identities: A XNOR 0 = NOT A and A XNOR 1 = A, so it too can act as a controlled inverter, just with the opposite sense to XOR.

Reset Delay

Mon, 01 Jan 0001 00:00:00 +0000

Reset Delay#

At power-up, a chip must be held in reset until its supply is stable, then released cleanly. Do this wrong and the device wakes into a garbage state, latches up, or resets erratically as the rail sags. The need is a reset that asserts while power is coming up and releases only once the supply is good — ideally with a defined delay.

The Right Answer: a Supervisor IC#

A dedicated reset supervisor (MAX809, MCP100/MCP809, TPS3839, and many others) is the proper part. It watches the supply voltage against a precise threshold, holds reset asserted whenever the rail is below it, and releases after a fixed delay once the rail is good — and, crucially, re-asserts on a brown-out if the supply dips later. Many include a watchdog input as well. This is what production designs use, because it handles the cases a naïve delay cannot.

Schmitt Trigger

Mon, 01 Jan 0001 00:00:00 +0000

Schmitt Trigger#

A Schmitt trigger is not a new logic function — it is usually just an inverter or buffer — but a special input characteristic: hysteresis. Instead of one switching threshold, it has two, and which one is active depends on which way the input is currently moving. That small change is what lets logic accept slow, noisy, or sloppy signals and still produce clean edges.

Two Thresholds Instead of One#

An ordinary gate has a single threshold, and any wobble of the input around that level produces a burst of output transitions. A Schmitt-trigger input has an upper threshold (V_T+) and a lower threshold (V_T−), with a gap between them: