DMA Transfer Patterns on Embedded Systems Development

DMA Channel & Stream Architecture

Mon, 01 Jan 0001 00:00:00 +0000

DMA Channel & Stream Architecture#

DMA controllers move data between peripherals and memory without CPU involvement, but the internal routing between a peripheral request and the DMA hardware that services it varies significantly across MCU families. Getting the mapping right is a prerequisite — configuring the wrong stream or channel produces no transfer and no error flag, just silence on the bus.

STM32F4: Streams, Channels, and Fixed Mapping#

The STM32F4 has two DMA controllers (DMA1 and DMA2), each with 8 streams (0–7). Each stream has a channel multiplexer that selects one of 8 channel inputs (0–7). The combination of controller, stream, and channel determines which peripheral request is serviced. These mappings are fixed in silicon and listed in the reference manual (RM0090, Table 42/43).

Memory-to-Peripheral & Peripheral-to-Memory

Mon, 01 Jan 0001 00:00:00 +0000

Memory-to-Peripheral & Peripheral-to-Memory#

Every DMA transfer has a source, a destination, and a set of rules governing how addresses advance and how data widths are matched. The three fundamental directions — peripheral-to-memory, memory-to-peripheral, and memory-to-memory — cover nearly every use case in embedded firmware. Getting the direction, increment mode, or data alignment wrong produces transfers that appear to work but deliver corrupted or shifted data.

Transfer Directions#

DMA direction is configured from the perspective of the DMA controller:

Circular & Double-Buffer Modes

Mon, 01 Jan 0001 00:00:00 +0000

Circular & Double-Buffer Modes#

Single-shot DMA transfers work for one-time operations like sending a command over SPI, but continuous data streams — ADC sampling, audio I/O, sensor logging — require the DMA controller to keep running indefinitely. Circular mode and double-buffer mode solve this by automatically reloading the transfer and providing mechanisms to process completed data without stopping the stream.

Circular Mode#

In circular mode, the DMA stream automatically reloads the transfer count (NDTR) and resets the memory pointer to the buffer base address when the current transfer completes. The stream never stops — it wraps around to the beginning of the buffer and continues filling.

Cache Coherency & DMA on Cortex-M7

Mon, 01 Jan 0001 00:00:00 +0000

Cache Coherency & DMA on Cortex-M7#

Cortex-M7 processors (STM32F7, STM32H7) include separate instruction and data caches — typically 16 KB I-cache and 16 KB D-cache — that dramatically improve execution speed by reducing access latency to main SRAM. But DMA controllers operate on the physical bus, bypassing the CPU cache entirely. When DMA writes data to SRAM, the CPU cache may still hold stale values at those addresses. When the CPU writes data that DMA will read, the cache may hold updated values that have not been flushed to SRAM. This coherency problem is the single most common source of intermittent, hard-to-diagnose data corruption on Cortex-M7 systems.