Interrupt Architecture & Firmware Patterns on Embedded Systems Development

NVIC Configuration & Priority Grouping

Mon, 01 Jan 0001 00:00:00 +0000

NVIC Configuration & Priority Grouping#

The Nested Vectored Interrupt Controller (NVIC) is the hardware block on every ARM Cortex-M processor that arbitrates between interrupt sources, determines which handler runs next, and manages preemption. On STM32F4 and STM32H7 devices, the NVIC implements 4 priority bits per interrupt, yielding 16 priority levels (0-15). Understanding how those bits divide between preemption priority and sub-priority — and what that division means for real-time behavior — is essential to building firmware that responds deterministically under load.

ISR Design Rules

Mon, 01 Jan 0001 00:00:00 +0000

ISR Design Rules#

An interrupt service routine (ISR) runs in exception context with elevated privileges and a hard constraint: every cycle spent inside the handler is a cycle that no other equal-or-lower-priority interrupt can execute. The fundamental design rule is to do the minimum work necessary — capture the event, copy the data, clear the flag — and defer everything else to the main loop or an RTOS task. Violating this rule produces systems that appear to work on the bench but fail under load, miss deadlines, or corrupt shared state in ways that only surface weeks into deployment.

Shared Data & Volatile Semantics

Mon, 01 Jan 0001 00:00:00 +0000

Shared Data & Volatile Semantics#

When a variable is written inside an ISR and read in the main loop (or vice versa), the compiler has no visibility into the asynchronous relationship between those two execution contexts. Without explicit annotation, the optimizer treats the main-loop code as the only thread of execution and may cache the variable in a register, reorder reads and writes, or eliminate accesses entirely. The volatile qualifier is the primary tool for preventing these optimizations, but it is both necessary in more places than most firmware expects and insufficient in others. Getting this right is the difference between firmware that works reliably and firmware that works only at -O0.

Critical Sections & Interrupt Masking

Mon, 01 Jan 0001 00:00:00 +0000

Critical Sections & Interrupt Masking#

A critical section is a region of code that must execute without interruption — either to protect shared data from concurrent access or to enforce timing guarantees on a sequence of operations. On Cortex-M, critical sections are implemented by masking interrupts: temporarily preventing the processor from responding to interrupt requests while the protected code executes. The cost is interrupt latency — every cycle spent with interrupts disabled is a cycle that incoming interrupts must wait. The design challenge is making critical sections as short as possible while still protecting everything that needs protection.