MOSFET Selection & Gate Drive#

The MOSFET is the workhorse switch in every motor drive, solenoid circuit, and power stage covered in this section. Selecting the right MOSFET means matching its voltage, current, and thermal ratings to the load — and then ensuring the gate drive circuit can switch it on and off fast enough to keep switching losses low. A MOSFET that looks perfect on the datasheet can fail in practice if the gate is driven too slowly, the thermal path is inadequate, or the parasitic inductance in the layout causes voltage spikes.

Key Selection Parameters#

RDS(on) — The Misleading Spec#

Datasheets specify RDS(on) at a specific VGS (usually 10 V) and temperature (25 °C). In practice:

• At VGS = 3.3 V (direct MCU drive), RDS(on) can be 2–5× the datasheet spec at VGS = 10 V
• RDS(on) increases with temperature: roughly +0.4 %/°C for silicon MOSFETs
• A FET with 10 mΩ at VGS=10V, 25°C may show 30–50 mΩ at VGS=3.3V, 100°C

Always check the RDS(on) vs VGS curve on the datasheet, not just the headline number.

Logic-Level MOSFETs#

For direct drive from 3.3 V MCU GPIOs, use MOSFETs specified as “logic level” — fully enhanced at VGS = 2.5–4.5 V:

Gate Driver ICs#

When the MCU cannot directly provide enough current to switch the MOSFET quickly, or when driving high-side N-channel FETs (which need VGS above the supply rail), a gate driver IC is required:

Why Gate Drive Current Matters#

The MOSFET gate is a capacitor (Ciss = Cgs + Cgd). Charging and discharging this capacitance through a resistance determines the switching speed:

t_rise ≈ Qg / I_drive

A MOSFET with Qg = 50 nC driven by a GPIO sourcing 10 mA takes ~5 µs to turn on — during which the FET is in its linear region, dissipating significant power. The same FET driven by a gate driver at 2 A turns on in ~25 ns.

Gate Resistor#

A small resistor (1–10 Ω) in series with the gate driver output limits the current peak and damps oscillation from parasitic inductance in the gate loop:

Gate driver output ── R_gate (4.7 Ω) ── MOSFET gate
                                         │
                                    R_gs (10 kΩ) pull-down
                                         │
                                       Source/GND

The pull-down resistor (10 kΩ) ensures the gate is discharged when the driver is unpowered or in high-impedance mode.

High-Side Drive#

Driving an N-channel MOSFET on the high side requires VGS > VDS — meaning the gate must be driven above the supply rail. Two approaches:

Bootstrap#

A capacitor charged from the low-side supply during the low-side FET’s on-time provides the elevated gate voltage. Covered in detail in H-Bridge Circuits.

Charge Pump#

Gate driver ICs with an integrated charge pump (e.g., LTC4440, NCP5181) generate a floating supply for the high-side gate without requiring a low-side on-time to refresh. Better for DC (100 % duty cycle) applications but limited in available current.

Tips#

• Select MOSFETs with VDS ≥ 2× the supply voltage. Inductive ringing and flyback spikes on the drain routinely reach 1.5× supply even with protection diodes.
• Check the RDS(on) at the actual gate drive voltage, not the headline specification at VGS=10 V. For 3.3 V direct drive, the SOA (safe operating area) curves and RDS(on) vs VGS plots are essential.
• Keep the gate drive loop (driver → gate → source → driver ground) as short as possible on the PCB. Inductance in this loop causes ringing on the gate signal, which can cause false turn-on of the complementary FET in an H-bridge (Miller effect).
• For MOSFETs switching at > 100 kHz, calculate switching losses (P_sw = 0.5 × VDS × ID × (t_on + t_off) × f_sw) in addition to conduction losses (P_cond = ID² × RDS(on)). At high frequencies, switching losses dominate.

Caveats#

• The MOSFET body diode has slow reverse recovery in many standard FETs. In bridge circuits, this causes a current spike when the complementary FET turns on. Select FETs with fast body diodes or add external Schottky diodes.
• VGS(th) on the datasheet is the threshold where the FET barely begins to conduct (typically at 250 µA). Full enhancement requires VGS significantly above this — typically VGS(th) + 2–4 V. A FET with VGS(th) = 2 V is not fully enhanced at 2 V.
• Parallel MOSFETs for higher current require matched gate resistors (one per FET) to ensure simultaneous switching. Without individual gate resistors, the FET with the lowest threshold carries all the current during switching transitions.
• ESD damage to the gate oxide is cumulative and invisible. A MOSFET that was handled without ESD precautions may work initially but have a reduced VGS(max) and fail unexpectedly under voltage stress.

In Practice#

• MOSFET runs very hot at modest current levels. The gate voltage is too low for full enhancement — the FET operates in its linear region, acting as a resistor rather than a switch. Measuring VDS while the FET is on (should be < 0.5 V at rated current) reveals the issue. Adding a gate driver or selecting a logic-level FET resolves the thermal problem.

• Oscilloscope shows ringing on the gate signal at each switching transition. Parasitic inductance in the gate loop (long traces, poor layout) resonates with the gate capacitance. The ringing can exceed VGS(max) and damage the gate oxide. Adding a gate resistor (4.7–10 Ω) damps the resonance; shortening the gate loop on the PCB eliminates it.

• MOSFET fails immediately when first powered on with no load. Gate drive voltage exceeds VGS(max) (±20 V for most FETs). This happens when a 12 V gate driver is used with a FET rated for ±12 V VGS, or when the bootstrap voltage adds to a high supply rail. Checking VGS with a scope before first power-on catches this.

• H-bridge has inconsistent dead time and occasional shoot-through. The high-side FET turns on faster than the low-side turns off (or vice versa) due to different gate charge requirements or asymmetric gate driver strengths. Adjusting individual gate resistor values to equalize switching times, or relying on the timer’s hardware dead-time generator, prevents the overlap.