<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Ethernet &amp; PoE on Embedded Systems Development</title><link>https://applied-ee.github.io/embedded/docs/networking/ethernet-poe/</link><description>Recent content in Ethernet &amp; PoE on Embedded Systems Development</description><generator>Hugo</generator><language>en-us</language><atom:link href="https://applied-ee.github.io/embedded/docs/networking/ethernet-poe/index.xml" rel="self" type="application/rss+xml"/><item><title>Ethernet PHY, MAC &amp; RMII/MII</title><link>https://applied-ee.github.io/embedded/docs/networking/ethernet-poe/ethernet-phy-mac/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/embedded/docs/networking/ethernet-poe/ethernet-phy-mac/</guid><description>&lt;h1 id="ethernet-phy-mac--rmiimii"&gt;Ethernet PHY, MAC &amp;amp; RMII/MII&lt;a class="anchor" href="#ethernet-phy-mac--rmiimii"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;Wired Ethernet on a microcontroller requires two functional blocks: a MAC (Media Access Controller) that handles frame construction, CRC generation, and DMA transfers, and a PHY (Physical Layer Transceiver) that converts digital signals to analog levels on the wire. Some MCUs integrate the MAC as a peripheral — STM32F4/F7/H7, i.MX RT1060, ESP32, SAM E70 — while others lack Ethernet entirely and rely on SPI-attached modules (covered separately). The PHY is almost always a discrete external chip, connected to the MAC through either the MII or RMII interface.&lt;/p&gt;</description></item><item><title>SPI Ethernet Modules</title><link>https://applied-ee.github.io/embedded/docs/networking/ethernet-poe/spi-ethernet-modules/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/embedded/docs/networking/ethernet-poe/spi-ethernet-modules/</guid><description>&lt;h1 id="spi-ethernet-modules"&gt;SPI Ethernet Modules&lt;a class="anchor" href="#spi-ethernet-modules"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;Not every MCU has an integrated Ethernet MAC. Many popular platforms — RP2040, STM32F1/L4, nRF52, ATmega — lack native Ethernet. SPI-attached Ethernet controllers bridge this gap by providing a complete MAC + PHY + magnetics interface accessible over a standard 4-wire SPI bus. Two chips dominate this space: the WIZnet W5500, which offloads the entire TCP/IP stack into hardware, and the Microchip ENC28J60, which provides only raw Ethernet frame access and relies on the host MCU to run a software TCP/IP stack like lwIP.&lt;/p&gt;</description></item><item><title>lwIP &amp; Embedded TCP/IP Stacks</title><link>https://applied-ee.github.io/embedded/docs/networking/ethernet-poe/lwip-tcpip-stack/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/embedded/docs/networking/ethernet-poe/lwip-tcpip-stack/</guid><description>&lt;h1 id="lwip--embedded-tcpip-stacks"&gt;lwIP &amp;amp; Embedded TCP/IP Stacks&lt;a class="anchor" href="#lwip--embedded-tcpip-stacks"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;lwIP (lightweight IP) is the dominant TCP/IP stack for bare-metal and RTOS-based microcontrollers. Written by Adam Dunkels and maintained as an open-source project, it runs on platforms with as little as 40 KB of RAM and provides a functional IPv4/IPv6 stack with TCP, UDP, DHCP, DNS, ICMP, IGMP, and ARP. ESP-IDF, STM32 CubeMX, NXP MCUXpresso, and TI SimpleLink all ship lwIP as their default network stack. Understanding its internal architecture — particularly the three API levels, memory management, and RTOS integration — is essential for debugging the throughput bottlenecks, memory leaks, and connection failures that inevitably arise in embedded networking.&lt;/p&gt;</description></item><item><title>Power over Ethernet: PD Design</title><link>https://applied-ee.github.io/embedded/docs/networking/ethernet-poe/poe-pd-design/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/embedded/docs/networking/ethernet-poe/poe-pd-design/</guid><description>&lt;h1 id="power-over-ethernet-pd-design"&gt;Power over Ethernet: PD Design&lt;a class="anchor" href="#power-over-ethernet-pd-design"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;Power over Ethernet (PoE) delivers both data and DC power over standard Ethernet cabling, eliminating the need for a separate power supply at the device. For embedded systems — IP cameras, access points, industrial sensors, building automation controllers — PoE simplifies installation to a single cable drop. The Powered Device (PD) is the equipment that receives power from the cable. Designing the PD side involves selecting the correct IEEE 802.3 power class, choosing a PD controller IC, implementing the detection and classification handshake, converting 48 V to the board&amp;rsquo;s operating voltages, meeting isolation requirements, and managing thermal dissipation.&lt;/p&gt;</description></item><item><title>Link Management &amp; Diagnostics</title><link>https://applied-ee.github.io/embedded/docs/networking/ethernet-poe/ethernet-link-management/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://applied-ee.github.io/embedded/docs/networking/ethernet-poe/ethernet-link-management/</guid><description>&lt;h1 id="link-management--diagnostics"&gt;Link Management &amp;amp; Diagnostics&lt;a class="anchor" href="#link-management--diagnostics"&gt;#&lt;/a&gt;&lt;/h1&gt;
&lt;p&gt;An Ethernet link is not a fire-and-forget connection. Cables get unplugged, switches reboot, duplex mismatches degrade throughput silently, and long cable runs develop faults over time. On MCU-based devices that often run unattended for months or years, robust link management — detecting link state changes, diagnosing failures, and recovering automatically — is as important as getting the initial connection working. The PHY provides the raw link status and diagnostic capabilities through MDIO registers; the firmware must poll or react to these signals and take appropriate action.&lt;/p&gt;</description></item></channel></rss>